The present application claims priority under 35 U.S.C. 119 to Korean Application No. 99-42332, which is hereby incorporated by reference in its entirety for all purposes.
1. Field of the Invention
The present invention relates to a semiconductor memory device, and more particularly, to a chip information output circuit capable of increasing layout efficiency without affecting input capacitance.
2. Description of the Related Art
Manufacturing processes of semiconductor memory devices are divided into manufacturing processes of the semiconductor memory devices in wafer state and processes related to assembling the device as a package. After the manufacturing processes of the semiconductor memory devices in the wafer state are completed, it is not possible to determine information regarding individual chips. Namely, it is not possible to know where the manufactured memory device is positioned on the wafer or on which wafer the manufactured memory device is positioned in a lot.
In order to solve this problem, a fuse box including a signature transistor and a fuse is conventionally provided. FIG. 1 is a circuit diagram showing a conventional fuse box. The fuse box 1 shown in FIG. 1 is arranged in each pin of the memory device. Fuses included in each of the pins are cut in the wafer state so as to have unique information regarding the chip. After subjecting a packaged memory device to certain conditions, it is determined whether the fuse is cut for each pin by measuring current which flows through the pin. When the states of whether the fuses are cut are observed for various pins, it is possible to obtain information regarding the chip.
For example, in the fuse box 1 shown in FIG. 1, in the case where none of the first through third fuses A, B, and C are cut, when a pad apply voltage, that is, an input voltage Vin is higher than the sum of a supply voltage Vcc and a transistor threshold voltage Vtn, a first transistor T1 is turned on and a certain amount of current I flows. If only the third fuse C is cut, the current I flows only when the input voltage Vin is higher than the supply voltage Vcc+2Vtn. Also, if the second fuse B and the third fuse C are cut, the current I flows only when the input voltage Vin is higher than the supply voltage Vcc+3Vtn. When the first fuse A is cut, the current I does not flow regardless of the input voltage Vin.
The states of the input voltage Vin and the output current I are determined according to the states, cut or not cut, of the fuses. When three fuses are used, four cases exist. For example, when it is assumed that such a fuse box is included in each pin of the memory device, it is possible to store 4N (N is the number of pins) information items regarding the chips.
However, because of the conventional fuse box 1 having the above structure, when the operating frequency of the memory device is greater than or equal to 400 MHZ and the memory device operates at high speed, input capacitance of each pin increases. Since signal integrity deteriorates due to the increase of the input capacitance, it is not possible to correctly receive a data signal value input to a memory device. Accordingly, the performance of the memory device may deteriorate.
Also, since the number of storable information items on the chips with respect to the number of fuses is only xc2xdN times of the maximum number of cases, a layout area becomes larger.
The present invention is therefore directed to providing a chip information output circuit which substantially overcomes one or more of the problems due to the limitations and disadvantages of the related art.
To solve the above problems, it is an object of the present invention to provide a chip information output circuit including a fuse box capable of reducing the layout area of a chip without affecting input capacitance.
Accordingly, to achieve the above object, there is provided a chip information output circuit, comprising a plurality of fuse blocks for generating different outputs according to whether a fuse is cut and a pipeline circuit for receiving a plurality of signals, which are output in parallel from the respective fuse blocks, and serially outputting the plurality of signals.
Each of the fuse blocks comprises a plurality of fuse boxes for generating output signals, the levels of which are either a high or low logic level according to whether the fuses included therein are cut, wherein the respective fuse boxes are enabled in response to the respective control signals and the output lines of the fuse boxes are wired by an OR operation.
The pipeline circuit comprises a plurality of serially connected latch units for latching signals output from the fuse blocks and outputting the latched signals. Each of the latch units comprises a multiplexer for selecting either data input from the fuse blocks or data input from adjacent latch units and outputting the selected data and a flip-flop for synchronizing the data output from the multiplexer with a clock signal and outputting the synchronized data.
According to a first preferred embodiment, each of the fuse boxes comprises a pull-up transistor gated by a ground voltage, the pull-up transistor for outputting a signal of a logic xe2x80x98highxe2x80x99 level to the drain thereof, a pull-down transistor gated by an input signal, the pull-down transistor for outputting a signal of a logic xe2x80x98lowxe2x80x99 level to the drain thereof, a fuse connected between the drain of the pull-up transistor and the drain of the pull-down transistor, and a transmission unit for transmitting a signal from the drain of the pull-up transistor to an output port in response to the input signal.
According to a second preferred embodiment, each of the fuse boxes comprises a pull-up transistor gated by an input signal, the pull-up transistor for outputting a signal of the logic xe2x80x98highxe2x80x99 level to the drain thereof, a fuse connected between a terminal to which the input signal is input and the drain of the pull-up transistor, and a transmission unit for transmitting a signal from the drain of the pull-up transistor to an output port in response to the input signal.
According to a third preferred embodiment, each of the fuse boxes comprises a pull-up transistor gated by an input signal, the pull-up transistor for outputting a signal of the logic xe2x80x98highxe2x80x99 level to the drain thereof, a pull-down transistor gated by the input signal, the pull-down transistor for outputting a signal of the logic xe2x80x98lowxe2x80x99 level to the drain thereof, a fuse connected between the drain of the pull-up transistor and the drain of the pull-down transistor, a latch for latching a signal from the drain of the pull-down transistor, and a transmission unit for transmitting the output signal of the latch to an output port in response to the input signal.
According to the present invention, it is possible to obtain information on a chip by storing information in a fuse box array which generates different outputs according to whether the fuse is cut and serially reading the information through a pin. Therefore, since it is possible to store 2N information items with respect to N fuse boxes without affecting input capacitance, it is possible to reduce the layout area using a minimum number of fuses.
Further scope of applicability of the present invention will become apparent from the detailed description given hereinafter. However, it should be understood that the detailed description and specific examples, while indicating preferred embodiments of the invention, are given by way of illustration only, since various changes and modifications within the spirit and scope of the invention will become apparent to those skilled in the art from this detailed description.